(1) Field of the Invention
This invention relates to monitoring and diagnostics of line processes used for the manufacture of semiconductor devices and more particularly to the design of product specific test chips.
(2) Description of prior art
Integrated circuits(ICs) are manufactured by first forming discrete semiconductor devices within the surface of silicon wafers. A multi-level metallurgical interconnection network is then formed over the devices contacting their active elements and wiring them together to create the desired circuits. The wiring layers are formed by first depositing an insulating layer over the discrete devices, patterning and etching contact openings into this layer, and then depositing conductive material into these openings. A conductive layer is then applied over the insulating layer which is then patterned and etched to form wiring interconnections between the device contacts thereby creating a first level of basic circuitry. These circuits are then further interconnected by utilizing additional wiring levels laid out over a additional insulating layers with via pass throughs.
Depending upon the complexity of the overall integrated circuit, one or two levels of patterned polysilicon conductors and two or more levels of metallurgy are required to form the necessary interconnections and to direct the wiring to pads which make the external connections for the completed chip. These patterns are formed by photolithographic masking techniques accompanied by reactive ion etching(RIE). The formation of such patterns invariably results in topographic features which effect the integrity of subsequently deposited layers, in particular when these layers are deposited by directional techniques such as sputtering or vacuum evaporation. Metal layers are typically deposited by such techniques.
Topographic features cause shadowing which results in poor edge coverage by the metal layer. When wiring patterns are subsequently etched in these layers, the regions of poor edge coverage are open or resistive, and likely to cause failure. Although various steps are taken to smooth out surface non-planarities, such as chemical mechanical polishing and thermally flowing of insulative glass layers, edge coverage problems still occur, As device geometries continue to shrink and deposited layers become thinner, process control must include testing integrity of these conductors.
In addition to the shadowing effects caused by topographic features, variations in device density over the surface of the wafer can cause processing variations. Differences in device density can cause local variations of processing rates which can cause some regions to be under processed and others to be over processed.
Whereas an integrated circuit chip may undergo a hundred or more discrete processing steps from starting wafer to finished chip, electrical testing of the chip itself is impossible until the chip is completed. Then only functionality tests may be done.
In order to monitor the step by step processing, parametric and defect test structures are used which are process step specific and can be tested between processing steps. During masterslice or front end of line(FEOL) processing, only parametric structures are used since actual devices are not yet formed. During the personalization or back end of line(BEOL) processing when the metal wiring levels are formed, testable structures may be conveniently formed and used to statistically evaluate find defects caused by particulate contamination. Processing steps such as photolithographic operations and plasma deposition and etching are particularly prone to defects caused by random particulate contamination which produces failure modes such as metal-to-metal shorts and opens. Interlevel shorts, and highly resistive or open vias and contacts.
Test structures for monitoring FEOL quantities such as implant resistivities, junction parameters and the like do not require large areas on the semiconductor wafer. They are frequently built into the saw kerf regions and are tested with probes during the FEOL processing.
Unlike parametric structures, the test structures required to examine the yield impact of random defect induced failure modes encountered in BEOL require larger semiconductor surface areas in order to give meaningful statistical information. Specifically, the structures which measure defect failure mechanisms must have critical areas comparable to those found on product chips. Thus, for example, a test structure which is designed to measure metal-to-metal shorts, must not only have an areas of adjacent metal lines comparable to such areas in the product but also there must be an adequate number of such structures present in order to provide statistically meaningful data.
In order to cope with these large area requirements a number of special die locations on each wafer may be allocated to these test structures. These are referred to as yield management test sites or simply as test chips. Clearly, their presence requires the sacrifice of valuable wafer area and they are either formed on separate test wafers inserted into jobs or they may occupy 3 to 6 chip locations on each product wafer. Statistical evaluations are made not at the wafer level but at the job level where an adequate sample size may be had.
The test structures themselves typically comprise mazes of serpentine metal or polysilicon lines, frequently with multiple taps, which correspond in width and spacing to lines on the product IC. These widths and spacings should generally reflect the dimensions found in the IC counterpart. The ends and taps of these lines are brought to probe pads which can be tested immediately after a metallization pattern is formed. The metal line mazes on a single metal level are tested for opens and shorts.
Test structures of various types for determining defect induced failure have been described. Comeau U.S. Pat. No. 5,329,228 describes a test chip which utilizes a transmission gate matrix which, when tested, provides information regarding a number of discrete failure types which can be attributed to certain processing steps. The structure can only be tested when the processing is complete. The process specific information such a test chip provides is only useful to point out serious process deviations to which much more timely alerts should be given. It is not cost effective to discover an process problem occurring at an early step with a test chip that must travel through the entire process.
Hsu U.S. Pat. No. 5,468,541 describes a test chip which looks at de-lamination of layers. This chip also engages the complete process and is then subjected to environmental stressing in order to discover processing problems. This test chip like that of Comeau are primary useful for evaluating chip and process design rather than for real-time process monitoring.
Integrated circuit chips contain various types of functional circuitry. The density if devices and wiring for each type can be quite different. This is particularly true for Dynamic-Random-Access-Memory(DRAM) where the density of wiring over the array portion of the chip is considerable different than that over the support circuitry. These variations affect some levels much more so than others. In addition the widths and spacings of the wiring over the array regions are different than those of the support circuits. Consequently the susceptibility of the array circuits to defect induced failures is different than that of the support circuits.
Shown in FIG. 1 is an example of a simple maze test structure formed on a wafer 10 from in a DRAM manufacturing process line. The maze is patterned in a first polysilicon layer which forms the gate electrodes of the product. The structure has two interlaced serpentine lines having a constant width and having probe pads at both ends of each line. For clarity, test line 101 is hatched differently than test line 102. Probe pads 103 and 104 are located at the ends of test line 101 and probe pads 105 an 106 are at the ends of test line 102. Optional pads 107 and 108 to taps are also shown. By themselves, the lines may be tested for opens and shorts. In this example, additional testing may be done to qualify a gate oxide which is formed beneath polysilicon lines 101 and 102 in the form of stripes 9 located between regions of field oxide 12. FIG. 2 is a cross section showing a polysilicon line 16 traversing one such gate oxide stripes 9.
By applying test probes between the polysilicon test lines 101 or 102 and the wafer 10, the integrity of the gate oxide 14 may also be determined immediately after the polysilicon 16 is patterned thereby providing timely data on, for example, gate oxide breakdown voltage.
Maze test structures of the type shown in FIG. 1, by virtue of their serpentine configuration, have a high critical area, and therefore a high sensitivity for random defects. By variation of the line widths and spacings, a size distribution of the random defects may be obtained. This information is valuable, not only for process development but for circuit design guidelines as well.
Although test structures such as the one shown in FIG. 1 and FIG. 2 can provide valuable data, their simplicity often belies more intricate and complex electrical consequences occurring in the product IC. These misrepresentations by the simple test structures become more pronounced as pattern and device dimensions shrink to sub-micron levels.
The parametric test structures, probed during FEOL, are essential in providing timely warning of tool malfunctions and other process irregularities, thereby permitting scrapping of out of spec wafers early on in the processing cycle. The serpentine, maze, and chain structures which can be tested after each metallization level, likewise provide timely information pointing out contaminated tools, etchant solutions and the like. The utilization of this type of process monitoring is essential to maintaining an efficient, high yielding, and cost effective manufacturing line.
There are, however, other process or design induced features which result in ultimate failure of integrated circuits. These may be classified as systematic or non-random failure mechanisms. Perhaps the simplest and easiest to comprehend systematic failure is the mask defect which will consistently cause a device failure and will not be flagged by the conventional test sites. Other types of systematic failures which manifest themselves particularly in present day ICs having varying degrees of circuit density and topology, cannot be properly detected by the simple conventional test sites.
Memory chips, for example, have large regions which consist of storage cell arrays. FIG. 2 is a plan view of the layout of a memory chip 120. The cell array 122 is serviced by sizeable peripheral logic circuits 124 known as address decoders. The device density and configuration in each of these regions on the chip are quite different. Line spacings and shapes as well as the surface topography are also different. During many types of processing steps these regions present differently to the process agents such as chemical etchants, plasmas, and the like. Consequently, local variations of processing rates occur which can result in systematic under processing in one region and over processing in another.
Yanagisawa et.al. U.S. Pat. No. 5,506,804 describes numerous testing procedures that may be done on a completed memory integrated circuit. This type of testing can reveal systematic defects in certain regions of the IC but in order to pinpoint process or design sources of these failures can require lengthy and costly physical unlayering of the failed chips. Process or design corrections could then be made. The time period between initial occurrence and repair of such defects could be enormous.
To find these failures and make process or design corrections in a timely fashion, test structures must be used which closely resemble a product IC in device density, pattern, and topology. For example, one may consider the process of etching a metal pattern using RIE. The etching time required to completely etch the pattern in a sparsely populated region of the IC chip may be considerably different from that in a region having a high density of metal lines. Such variations in feature density and topology are commonplace in the manufacture of DRAMs where the density and topology of features in the peripheral support circuitry is significantly different from that in the array area. Thus, while some regions of the chip may be properly etched, others areas may have residual pockets of metal which may produce shorts.
The causes of these pattern sensitive effects are varied. In instances where chemical processing is involved they are likely to be caused by a loading effect wherein reactant depletion occurs or topological features alter reactant accessibility. The effect of regions of different feature density and topology on processing characteristics is sometimes referred to as the global proximity effect. Simple parametric or maze type defect density structures described hereinbefore are not adequate for revealing such systematic problems.
The test structures required to address failure modes such as caused by the global proximity effect, must therefore resemble the product in great detail while at the same time be capable of measurement during the wafer process cycle. These test structures must be product specific and, at best, a single set of test structures could be associated with a class of closely related products.
Fortunately the ICs which are most affected by systematic processing problems are the ones which lend themselves best to the use of product specific test sites to address them. This invention deals with the use of product specific test chips in the manufacture of high density memories.
A portion of a current cell design for a stacked capacitor(STC) DRAM having diagonal active areas and a capacitor design similar to that of Dennison U.S. Pat. No. 5,292,677 is shown in cross section by FIG. 3 and in a top view by FIG. 4.
Referring first to FIG. 3, two storage capacitors 36, of a tubular design, are shown formed on a silicon wafer 10. The lower, storage plates 24 contact the source diffusions 18 of two adjacent metal oxide field effect transistors (MOSFET)s whose gates 16 comprise polysilicon wordlines. The bitline 40 connects to the common drain 20 of the two MOSFETs. The polysilicon wordlines 16 located over field oxide regions 12 service other MOSFETS located in the array above and below the plane of the page. Inter-polysilicon-insulator (IPO) layers 14 and 22 support and insulate the large area portions of the capacitors 36 above the wordline/bitline array. The capacitor dielectric, typically, a composite layer of SiO.sub.2 /Si.sub.3 N.sub.4 /SiO.sub.2 (ONO) 25, is covered by the upper cell plate 26 which spans a plurality of cells.
An inter-level-dielectric (ILD) layer 28 insulates the upper cell plate 26 from a subsequently deposited metal layer, which becomes the first level of wiring for the DRAM circuits. Contacts, formed through openings in the ILD connect it to the circuit elements. Most of these contacts are directed to the peripheral circuitry of the DRAM.
Referring now to FIG. 4, a top view of the DRAM cell array is shown. The cross section of FIG. 4 through the line 3-3' is shown in FIG. 3. The active regions 11, are diagonally disposed to the perpendicular wordlines 16 and bitlines 40. The contact regions of the bitlines 17 and of the capacitor storage plates 19 to the active regions are shown.
This invention teaches the use of structures which closely resemble the cell array of a DRAM IC and can be tested during processing. The structures reflect the complexity and topology of the product cell array to signal systematic process aberrations as well as design defects which cause device failures.